Design of Architecture and FPGA Implementation of a Video Encoder

This paper proposes a novel VLSI architecture for Video Encoder, which processes high resolution video sequences at real time rates. The architecture has been realized using Verilog and implemented on an Xilinx XUPVP30 FPGA. The gate count of the implementation is approximately 800,000 including an output FIFO of size 128 K bits. It can process 1600x1200 pixels color motion pictures in 4:2:0 format at 30 frames per second as per MPEG-2 standard. The compression effected is typically 20 to 40 and the reconstructed picture is of good quality with a PSNR values of 32 dB or more. The main advantage of the architecture proposed is that it improves the throughput by over 30% compared to the earlier Encoder developed by one of the present authors. The proposed architecture of Video Encoder consists of Discrete Cosine Transform and Quantization Processor, Run Length Encoder, Variable Length Coder, Header Generator, Serializer, FIFOs and a Master Controller that co-ordinates all the activities of the encoder. The Video Encoder has also been coded in Matlab in order to validate the Verilog realization.